Source synchronous multi-lane parallel interface communication links can suffer from timing margin issues due to skew between respective lanes of the link. One of the main sources of skew is due to distributing a received clock to corresponding parallel receiver data channels. Such skew increases as the number of data channels increases. Similarly, skew contribution will be more significant as communication speeds increase. High levels of skew in a receiver can cause the receiver to exceed a skew budget and further to decrease system AC margin timing, both of which can adversely affect performance.